VHDL Code for D Flip Flop

Library IEEE;
USE IEEE std_logic_1164.all;
Entity D_Flip_Flop is
port(D,clr,pre,clk : IN std_logic ;
         nq : Out Std_logic;
           q : inout std_logic);
End D_Flip_Flop;

Architecture behavioral of D_Flip_Flop is
begin
process (clk,pre,clr)
begin
if ( pre = '0' and clr = '1' ) then q <= '1' ;
elsif ( pre = '1' and clr = '0') then q <= '0' ;
elsif ( clk' event and clk = '1') then q <= d ;
end if ;
end process ;
nq <= not q;
end behavioral ;

The respective Block diagram TTL Schematic and RTL Schematic are given below