Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
Entity Comparator is
port(a,b : in std_logic_vector(3 downto 0);
eq,lr,gr : Out std_logic);
End Comparator;
Friday, 1 September 2017
4 Bit Comparator VHDL Code
Architecture Behavioral of comparator is
begin
process (a,b)
begin
eq<= '0' ; gr<= '0' ; lr<= '0';
if (a=b) then eq<= '1' ;
end if;
if (a>b) then gr<= '1' ;
end if;
if (a<b) then lr<= '1' ;
end if;
end process;
end behavioral;
begin
process (a,b)
begin
eq<= '0' ; gr<= '0' ; lr<= '0';
if (a=b) then eq<= '1' ;
end if;
if (a>b) then gr<= '1' ;
end if;
if (a<b) then lr<= '1' ;
end if;
end process;
end behavioral;
The Respective Block diagram TTL Schematic and RTL Schematic are given below
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| VHDL Code |
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| Block Diagram |
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| TTL Schematic |
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| RTL schematic |
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