Library IEEE;
USE IEEE std_logic_1164.all;
Entity Decade is
port (clk,rst : IN std_logic;
q : OUT std_logic_vector (3 downto 0);
End Decade;
Architecture Behavioral of Decade is
Signal count : std_logic_vector (3 downto 0);
begin
Process (clk,rst)
begin
if (rst = '0') then count <= "0000" ;
elsif (clk' event and clk = '1') then
count = count+1;
end if;
if (count = "1010") then count <= "0000" ;
end if;
end process;
q <= count ;
End behavioral;
Library IEEE;
USE IEEE std_logic_1164.all;
Entity Counter is
port (clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic_vector(3 downto 0);
End Counter;
Architecture Behavioral of Counter is
Signal count : std_logic_vector(3 downto 0);
begin
Process (clk,rst)
begin
if (rst = '1') then count <= "0000";
elsif (clk' event and clk = '1') then
count <= count+1;
end if;
if (count = "1111") then count <= "0000";
end if;
end process;
q <= count ;
end behavioral;
Library IEEE;
USE IEEE std_logic_1164.all;
Entity D_Flip_Flop is
port(D,clr,pre,clk : IN std_logic ;
nq : Out Std_logic;
q : inout std_logic);
End D_Flip_Flop;
Architecture behavioral of D_Flip_Flop is
begin
process (clk,pre,clr)
begin
if ( pre = '0' and clr = '1' ) then q <= '1' ;
elsif ( pre = '1' and clr = '0') then q <= '0' ;
elsif ( clk' event and clk = '1') then q <= d ;
end if ;
end process ;
nq <= not q;
end behavioral ;
The respective Block diagram TTL Schematic and RTL Schematic are given below
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| VHDL Code |
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| Block Diagram |
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| TTL Schematic |
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| RTL schematic |
