4 Bit Counter VHDL Code

Library IEEE;
USE IEEE std_logic_1164.all;
Entity Counter is
port (clk : IN std_logic;
         rst : IN std_logic;
            q : OUT std_logic_vector(3 downto 0);
End Counter;
Architecture Behavioral of Counter is
Signal count : std_logic_vector(3 downto 0);
begin
Process (clk,rst)
begin
if (rst = '1') then count <= "0000";
elsif  (clk' event and clk = '1') then
count <= count+1;
end if;
if (count = "1111") then count <= "0000";
end if;
end process;
q <= count ;
end behavioral;